View MCP6284T-ESLDAA_8712480.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 2008 microchip technology inc. ds21811e-page 1 mcp6281/1r/2/3/4/5 features gain bandwidth product: 5 mhz (typical) supply current: i q = 450 a (typical) supply voltage: 2.2v to 6.0v rail-to-rail input/output extended temperature range: -40c to +125c available in single, dual, and quad packages single with c s ( mcp6283 ) dual with c s ( mcp6285 ) applications automotive portable equipment photodiode amplifier analog filters notebooks and pdas battery-powered systems design aids spice macro models filterlab ? software mindi? circuit designer & simulator maps (microchip advanced part selector) analog demonstration and evaluation boards application notes description the microchip technology inc. mcp6281/1r/2/3/4/5 family of operational amplifiers (op amps) provide wide bandwidth for the current. th is family has a 5 mhz gain bandwidth product (gbwp) and a 65 phase margin. this family also operates from a single supply voltage as low as 2.2v, while drawing 450 a (typical) quiescent current. additionally, the mcp6281/1r/2/3/4/5 supports rail-to-rail input and output swing, with a common mode input voltage range of v dd +300mv to v ss C 300 mv. this family of operational amplifiers is designed with microchips advanced cmos process. the mcp6285 has a chip select (cs ) input for dual op amps in an 8-pin package. this device is manufactured by cascading the two op amps (the output of op amp a connected to the non-inverting input of op amp b). the cs input puts the device in low-power mode. the mcp6281/1r/2/3/4/5 family operates over the extended temperature range of -40c to +125c. it also has a power supply range of 2.2v to 6.0v. package types v in _ mcp6281 v dd 1 2 3 4 8 7 6 5 - + nc nc nc v in + v ss mcp6282 pdip, soic, msop mcp6284 1 2 3 4 14 13 12 11 - + - + 10 98 5 6 7 + - - + pdip, soic, tssop 1 2 3 4 8 7 6 5 - + - + v out mcp6283 1 2 3 4 8 7 6 5 - + v ina _ v ina + v ss v outa v outb v dd v inb _ v inb + v ss v in + v in _ nc cs v dd v out nc v outa v ina _ v ina + v dd v ss v outb v inb _ v inb + v outc v inc _ v inc + v outd v ind _ v ind + pdip, soic, msop pdip, soic, msop mcp6285 pdip, soic, msop 1 2 3 4 8 7 6 5 + - v ina _ v ina + v ss v outa /v inb + v outb v dd v inb _ cs - + mcp6281 sot-23-5 4 1 2 3 - + 5 v dd v in C v out v ss v in + mcp6281r sot-23-5 4 1 2 3 - + 5 v ss v in C v out v dd v in + mcp6283 sot-23-6 4 1 2 3 - + 6 5 v ss v in + v out cs v dd v in _ 450 a, 5 mhz rail-to-rail op amp downloaded from: http:///
mcp6281/1r/2/3/4/5 ds21811e-page 2 ? 2008 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings ? v dd Cv ss ........................................................................7.0v current at input pins ....................................................2 ma analog inputs (v in +, v in C) ?? ........ v ss C1.0vtov dd +1.0v all other inputs and outputs ......... v ss C 0.3v to v dd +0.3v difference input voltage ...................................... |v dd Cv ss | output short circuit current .................................continuous current at output and supply pins ............................30 ma storage temperature....................................C65c to +150c maximum junction temperature (t j ) ......................... .+150c esd protection on all pins (hbm; mm) .............. 4 kv; 400v ? notice: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rati ng only and functional operation of the device at those or any other conditions above those indicated in the operational listi ngs of this specification is not implied. exposure to maximu m rating conditions for extended periods may affect device reliability. ?? see section 4.1.2 input voltage and current limits . dc electrical specifications electrical characteristics : unless otherwise indicated, t a = +25 c, v dd = +2.2v to +5.5v, v ss =gnd, v out v dd /2, v cm = v dd /2, v l = v dd /2, r l = 10 k to v l and cs is tied low. (refer to figure 1-2 and figure 1-3 ). parameters sym min typ max units conditions input offset input offset voltage v os -3.0 +3.0 mv v cm = v ss (note 1) input offset voltage (extended temperature) v os -5.0 +5.0 mv t a = -40c to +125c, v cm = v ss (note 1) input offset temperature drift v os / t a 1 . 7 v / c t a = -40c to +125c, v cm = v ss (note 1) power supply rejection ratio psrr 70 90 db v cm = v ss (note 1) input bias, input offset current and impedance input bias current i b 1.0 pa note 2 at temperature i b 50 200 pa t a = +85c (note 2) at temperature i b 2 5n a t a = +125c (note 2) input offset current i os 1.0 pa note 3 common mode input impedance z cm 1 0 13 ||6 ||pf note 3 differential input impedance z diff 1 0 13 ||3 ||pf note 3 common mode (note 4) common mode input range v cmr v ss ? 0.3 v dd + 0.3 v common mode rejection ratio cmrr 70 85 db v cm = -0.3v to 2.5v, v dd = 5v common mode rejection ratio cmrr 65 80 db v cm = -0.3v to 5.3v, v dd = 5v open-loop gain dc open-loop gain (large signal) a ol 90 110 db v out = 0.2v to v dd C 0.2v, v cm =v ss (note 1) output maximum output voltage swing v ol , v oh v ss + 15 v dd C 15 mv 0.5v input overdrive output short circuit current i sc 2 5m a power supply supply voltage v dd 2.2 6.0 v (note 5) quiescent current per amplifier i q 300 450 570 a i o = 0 note 1: the mcp6285s v cm for op amp b (pins v outa /v inb + and v inb C) is v ss + 100 mv. 2: the current at the mcp6285s v inb C pin is specified by i b only. 3: this specification does not apply to the mcp6285s v outa /v inb + pin. 4: the mcp6285s v inb C pin (op amp b) has a common mode range (v cmr ) of v ss + 100 mv to v dd C 100 mv. the mcp6285s v outa /v inb + pin (op amp b) has a voltage range specified by v oh and v ol . 5: all parts with date codes november 2007 and la ter have been screened to ensure operation at v dd = 6.0v. however, the other minimum and maximum specifications are measured at 2.4v and/or 5.5v. downloaded from: http:///
? 2008 microchip technology inc. ds21811e-page 3 mcp6281/1r/2/3/4/5 ac electrical specifications mcp6283/mcp6285 ch ip select (cs ) specifications figure 1-1: timing diagram for the chip select (cs) pin on the mcp6283 and mcp6285. electrical characteristics: unless otherwise indicated, t a = +25c, v dd = +2.2v to +5.5v, v ss = gnd, v out v dd /2, v cm = v dd /2, v l = v dd /2, r l = 10 k to v l , c l = 60 pf and cs is tied low. (refer to figure 1-2 and figure 1-3 ). parameters sym min typ max units conditions ac response gain bandwidth product gbwp 5.0 mhz phase margin at unity-gain pm 65 g = +1 v/v slew rate sr 2.5 v/s noise input noise voltage e ni 5 . 2 v p-p f = 0.1 hz to 10 hz input noise voltage density e ni 1 6n v / hz f = 1 khz input noise current density i ni 3f a / hz f = 1 khz electrical characteristics: unless otherwise indicated, t a = +25c, v dd = +2.2v to +5.5v, v ss = gnd, v out v dd /2, v cm = v dd /2, v l = v dd /2, r l = 10 k to v l , c l = 60 pf and cs is tied low. (refer to figure 1-2 and figure 1-3 ). parameters sym min typ max units conditions cs low specifications cs logic threshold, low v il v ss 0 . 2 v dd v cs input current, low i csl 0 . 0 1 ac s = v ss cs high specifications cs logic threshold, high v ih 0.8 v dd v dd v cs input current, high i csh 0 . 7 2 ac s = v dd gnd current per amplifier i ss - 0 . 7 ac s = v dd amplifier output leakage 0.01 a cs = v dd dynamic specifications (note 1) cs low to valid amplifier output, turn-on time t on 41 0 s c s low 0.2 v dd , g = +1 v/v, v in = v dd /2, v out = 0.9 v dd /2, v dd = 5.0v cs high to amplifier output high-z t off 0 . 0 1 sc s high 0.8 v dd , g = +1 v/v, v in = v dd /2, v out = 0.1 v dd /2 hysteresis v hyst 0 . 6 vv dd = 5v note 1: the input condition (v in ) specified applies to both op amp a and b of the mcp6285. the dynamic s pecification is tested at the output of op amp b (v outb ). v il hi-z t on v ih cs t off v out -0.7 a hi-z i ss i cs 0.7 a 0.7 a -0.7 a -450 a 10 na (typical) (typical) (typical) (typical) (typical) (typical) downloaded from: http:///
mcp6281/1r/2/3/4/5 ds21811e-page 4 ? 2008 microchip technology inc. temperature specifications 1.1 test circuits the test circuits used for the dc and ac tests are shown in figure 1-2 and figure 1-2 . the bypass capacitors are laid out according to the rules discussed in section 4.6 supply bypass . figure 1-2: ac and dc test circuit for most non-inverting gain conditions. figure 1-3: ac and dc test circuit for most inverting gain conditions. electrical characteristics: unless otherwise indicated, v dd = +2.2v to +5.5v and v ss = gnd. parameters sym min typ max units conditions temperature ranges operating temperature range t a -40 +125 c note storage temperature range t a -65 +150 c thermal package resistances thermal resistance, 5l-sot-23 ja 256 c/w thermal resistance, 6l-sot-23 ja 230 c/w thermal resistance, 8l-pdip ja 8 5 c / w thermal resistance, 8l-soic ja 163 c/w thermal resistance, 8l-msop ja 206 c/w thermal resistance, 14l-pdip ja 70 c/w thermal resistance, 14l-soic ja 120 c/w thermal resistance, 14l-tssop ja 100 c/w note: the junction temperature (t j ) must not exceed the absolute maximum specification of +150c. v dd mcp628x r g r f r n v out v in v dd /2 1f c l r l v l 0.1 f v dd mcp628x r g r f r n v out v dd /2 v in 1f c l r l v l 0.1 f downloaded from: http:///
? 2008 microchip technology inc. ds21811e-page 5 mcp6281/1r/2/3/4/5 2.0 typical performance curves note: unless otherwise indicated, t a = +25c, v dd = +2.2v to +6.0v, v ss = gnd, v cm = v dd /2, v out v dd /2, v l = v dd /2, r l = 10 k to v l , c l = 60 pf and cs is tied low. figure 2-1: input offset voltage. figure 2-2: input bias current at t a =+85 c. figure 2-3: input offset voltage vs. common mode input voltage at v dd = 2.2v. figure 2-4: input offset voltage drift. figure 2-5: input bias current at t a = +125 c. figure 2-6: input offset voltage vs. common mode input voltage at v dd = 5.5v. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purpose s only. the performance characteristics listed herein are not tested or guaranteed. in so me graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power suppl y range) and therefore outs ide the warranted range. 0% 2% 4% 6% 8% 10% 12% 14% -2.8-2.4 -2.0 -1.6 -1.2 -0.8 -0.4 0.00.4 0.8 1.2 1.6 2.0 2.4 2.8 input offset voltage (mv) percentage of occurrences 832 samples v cm = v ss 0% 5% 10% 15% 20% 25% 0 102030405060708090100 input bias current (pa) percentage of occurrences 210 samples t a = +85c -100 -50 0 50 100 150 200 250 300 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 common mode input voltage (v) input offset voltage (v) v dd = 2.2v t a = +125c t a = +85c t a = +25c t a = -40c 0% 5% 10% 15% 20% 25% 30% -10-8-6-4-20246810 input offset voltage drift (v/c) percentage of occurrences 832 samples v cm = v ss t a = -40c to +125c 0% 5% 10% 15% 20% 25% 30% 35% 0 200 400 800 1200 1600 2000 2400 2800 3200 3600 input bias current (pa) percentage of occurrences 210 samples t a = +125c -100 -50 0 50 100 150 200 250 300 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 common mode input voltage (v) input offset voltage (v) v dd = 5.5v t a = +125c t a = +85c t a = +25c t a = -40c downloaded from: http:///
mcp6281/1r/2/3/4/5 ds21811e-page 6 ? 2008 microchip technology inc. typical performance curves (continued) note: unless otherwise indicated, t a = +25c, v dd = +2.2v to +6.0v, v ss = gnd, v cm = v dd /2, v out v dd /2, v l = v dd /2, r l = 10 k to v l , c l = 60 pf and cs is tied low. figure 2-7: input offset voltage vs. output voltage. figure 2-8: cmrr, psrr vs. frequency. figure 2-9: input bias, offs et currents vs. common mode input voltage at t a =+85c. figure 2-10: input bias, input offset currents vs. ambient temperature. figure 2-11: cmrr, psrr vs. ambient temperature. figure 2-12: input bias, offset currents vs. common mode input voltage at t a = +125c. -100 -50 0 50 100 150 200 250 300 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 output voltage (v) input offset voltage (v) v dd = 2.2v v cm = v ss representative part v dd = 5.5v 20 30 40 50 60 70 80 90 100 110 1.e+00 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 frequency (hz) cmrr, psrr (db) 1 10k 100k 1m 100 10 1k psrr+ psrr- cmrr -25 -15 -5 5 15 25 35 45 55 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 common mode input voltage (v) input bias, offset currents (pa) t a = +85c v dd = 5.5v input bias current input offset current 1 10 100 1,000 10,000 25 35 45 55 65 75 85 95 105 115 125 ambient temperature (c) input bias, offset currents (pa) input bias current input offset current v cm = v dd v dd = 5.5v 60 70 80 90 100 110 120 -50 -25 0 25 50 75 100 125 ambient temperature (c) psrr, cmrr (db) psrrv cm = v ss cmrr -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 common mode input voltage (v) input bias, offset currents (na) t a = +125c v dd = 5.5v input bias current input offset current downloaded from: http:///
? 2008 microchip technology inc. ds21811e-page 7 mcp6281/1r/2/3/4/5 typical performance curves (continued) note: unless otherwise indicated, t a = +25c, v dd = +2.2v to +6.0v, v ss = gnd, v cm = v dd /2, v out v dd /2, v l = v dd /2, r l = 10 k to v l , c l = 60 pf and cs is tied low. figure 2-13: quiescent current vs. power supply voltage. figure 2-14: open-loop gain, phase vs. frequency. figure 2-15: maximum output voltage swing vs. frequency. figure 2-16: output voltage headroom vs. output current magnitude. figure 2-17: gain bandwidth product, phase margin vs. ambient temperature. figure 2-18: slew rate vs. ambient temperature. 0 100 200 300 400 500 600 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5. 5 power supply voltage (v) quiescent current (a/amplifier) t a = +125c t a = +85c t a = +25c t a = -40c -20 0 20 40 60 80 100 120 1.e-01 1.e+00 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 1.e+08 frequency (hz) open-loop gain (db) -210 -180 -150 -120 -90 -60 -30 0 open-loop phase () gain phase 0.1 1 10 100 1k 10k 100k 1m 10m 100m 0.1 1 10 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 frequency (hz) maximum output voltage swing (v p-p ) v dd = 2.2v 1k 10k 100k 1m v dd = 5.5v 10m 1 10 100 1000 0.01 0.1 1 10 output current magnitude (ma) ouput voltage headroom (mv) v ol - v ss v dd - v oh 0 1 2 3 4 5 6 -50-25 0 255075100125 ambient temperature (c) gain bandwidth product (mhz) 60 65 70 75 80 85 90 phase margin () gain bandwidth product v dd = 5.5v v dd = 2.2v v dd = 2.2v v dd = 5.5v phase margin 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 -50 -25 0 25 50 75 100 125 ambient temperature (c) slew rate (v/s) rising edge, v dd = 2.2v rising edge, v dd = 5.5v falling edge, v dd = 5.5v falling edge, v dd = 2.2v downloaded from: http:///
mcp6281/1r/2/3/4/5 ds21811e-page 8 ? 2008 microchip technology inc. typical performance curves (continued) note: unless otherwise indicated, t a = +25c, v dd = +2.2v to +6.0v, v ss = gnd, v cm = v dd /2, v out v dd /2, v l = v dd /2, r l = 10 k to v l , c l = 60 pf and cs is tied low. figure 2-19: input noise voltage density vs. frequency. figure 2-20: output short circuit current vs. power supply voltage. figure 2-21: quiescent current vs. chip select (cs ) voltage at v dd = 2.2v (mcp6283 and mcp6285 only). figure 2-22: input noise voltage density vs. common mode input voltage at 1 khz. figure 2-23: channel-to-channel separation vs. frequency (mcp6282 and mcp6284 only). figure 2-24: quiescent current vs. chip select (cs ) voltage at v dd = 5.5v (mcp6283 and mcp6285 only). 10 100 1,000 1.e-01 1.e+00 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 frequency (hz) input noise voltage density (nv/ hz) 0.1 100 10 1k 100k 10k 1m 1 0 5 10 15 20 25 30 35 0.00.51.01.52.02.53.03.54.04.55.05.5 power supply voltage (v) ouptut short circuit current (ma) t a = +125c t a = +85c t a = +25c t a = -40c 0 50 100 150 200 250 300 350 400 450 500 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 chip select voltage (v) quiescent current (a/amplifier) hysteresis op-amp shuts off here op-amp turns on here v dd = 2.2v cs swept high to low cs swept low to high 0 5 10 15 20 25 30 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 common mode input voltage (v) input noise voltage density (nv/ hz) f = 1 khz v dd = 5.0v 100 110 120 130 140 1 10 100 frequency (khz) channel-to-channel separation (db) 0 100 200 300 400 500 600 700 800 900 1000 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 chip select voltage (v) quiescent current (a/amplifier) hysteresis op amp toggles on/off here v dd = 5.5v cs swept low to high cs swept high to low downloaded from: http:///
? 2008 microchip technology inc. ds21811e-page 9 mcp6281/1r/2/3/4/5 typical performance curves (continued) note: unless otherwise indicated, t a = +25c, v dd = +2.2v to +6.0v, v ss = gnd, v cm = v dd /2, v out v dd /2, v l = v dd /2, r l = 10 k to v l , c l = 60 pf and cs is tied low. figure 2-25: large-signal, non-inverting pulse response. figure 2-26: small-signal, non-inverting pulse response. figure 2-27: chip select (cs ) to amplifier output re sponse time at v dd = 2.2v (mcp6283 and mcp6285 only). figure 2-28: large-signal, inverting pulse response. figure 2-29: small-signal, inverting pulse response. figure 2-30: chip select (cs ) to amplifier output re sponse time at v dd = 5.5v (mcp6283 and mcp6285 only). 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.e+00 2.e-06 4.e-06 6.e-06 8.e-06 1.e-05 1.e-05 1.e-05 2.e-05 2.e-05 2.e-05 time (2 s/div) output voltage (v) g = +1v/v v dd = 5.0v time (500 ns/div) output voltage (10 mv/div) g = +1v/v 0.0 0.5 1.0 1.5 2.0 2.5 0.0e+00 5.0e-06 1.0e-05 1.5e-05 2.0e-05 2.5e-05 3.0e-05 3.5e-05 4.0e-05 4.5e-05 5.0e-0 5 time (5 s/div) chip select, output voltages (v) v out output on output high-z v dd = 2.2v g = +1v/v v in = v ss cs voltage 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.e+00 2.e-06 4.e-06 6.e-06 8.e-06 1.e-05 1.e-05 1.e-05 2.e-05 2.e-05 2.e-0 5 time (2 s/div) output voltage (v) g = -1v/v v dd = 5.0v time (500 ns/div) output voltage (10 mv/div) g = -1v/v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0.e+00 5.e-06 1.e-05 2.e-05 2.e-05 3.e-05 3.e-05 4.e-05 4.e-05 5.e-05 5.e- 05 time (5 s/div) chip select, output voltages (v) v out output on output high-z v dd = 5.5v g = +1v/v v in = v ss cs voltage downloaded from: http:///
mcp6281/1r/2/3/4/5 ds21811e-page 10 ? 2008 microchip technology inc. note: unless otherwise indicated, t a = +25c, v dd = +2.2v to +6.0v, v ss = gnd, v cm = v dd /2, v out v dd /2, v l = v dd /2, r l = 10 k to v l , c l = 60 pf and cs is tied low. figure 2-31: measured input current vs. input voltage (below v ss ). figure 2-32: the mcp6281/1r/2/3/4/5 show no phase reversal. 1.e-12 1.e-11 1.e-10 1.e-09 1.e-08 1.e-07 1.e-06 1.e-05 1.e-04 1.e-03 1.e-02 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 input voltage (v) input current magnitude (a) +125c +85c +25c -40c 10m 1m 100 10 1 100n 10n 1n 100p 10p 1p -1 0 1 2 3 4 5 6 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 time (1 ms/div) input, output voltage (v) v dd = 5.0v g = +2 v/v v in v out downloaded from: http:///
? 2008 microchip technology inc. ds21811e-page 11 mcp6281/1r/2/3/4/5 3.0 pin descriptions descriptions of the pins are listed in table 3-1 (single op amps) and table 3-2 (dual and quad op amps). table 3-1: pin function table for single op amps table 3-2: pin function table for dual and quad op amps 3.1 analog outputs the output pins are low-impedance voltage sources. 3.2 analog inputs the non-inverting and inverting inputs are high- impedance cmos inputs with low bias currents. 3.3 mcp6285s v outa /v inb + pin for the mcp6285 only, the output of op amp a is connected directly to the non-inverting input of op amp b; this is the v outa /v inb + pin. this connection makes it possible to provide a chip select pin for duals in 8-pin packages. 3.4 chip select digital input (cs) this is a cmos, schmitt-triggered input that places the part into a low-power mode of operation. 3.5 power supply pins the positive power supply (v dd ) is 2.2v to 6.0v higher than the negative power supply (v ss ). for normal operation, the other pins are between v ss and v dd . typically, these parts are used in a single (positive) supply configuration. in this case, v ss is connected to ground and v dd is connected to the supply. v dd will need bypass capacitors. mcp6281 mcp6281r mcp6283 symbol description pdip, soic, msop sot-23-5 sot-23-5 pdip, soic, msop sot-23-6 611 6 1 v out analog output 244 2 4v in C inverting input 333 3 3v in + non-inverting input 752 7 6v dd positive power supply 425 4 2v ss negative power supply 8 5c s chip select 1,5,8 1,5 nc no internal connection mcp6282 mcp6284 mcp6285 symbol description pdip, soic, msop pdip, soic, tssop pdip, soic, msop 11 v outa analog output (op amp a) 222 v ina C inverting input (op amp a) 333 v ina + non-inverting input (op amp a) 848 v dd positive power supply 55 v inb + non-inverting input (op amp b) 666 v inb C inverting input (op amp b) 777 v outb analog output (op amp b) 8 v outc analog output (op amp c) 9 v inc C inverting input (op amp c) 1 0 v inc + non-inverting input (op amp c) 41 14 v ss negative power supply 1 2 v ind + non-inverting input (op amp d) 1 3 v ind C inverting input (op amp d) 1 4 v outd analog output (op amp d) 1 v outa / v inb + analog output (op amp a)/non- inverting input (op amp b) 5 c s chip select downloaded from: http:///
mcp6281/1r/2/3/4/5 ds21811e-page 12 ? 2008 microchip technology inc. 4.0 application information the mcp6281/1r/2/3/4/5 family of op amps is manu- factured using microchip's state-of-the-art cmos process. this family is specifically designed for low- cost, low-power and general purpose applications. the low supply voltage, low quiescent current and wide bandwidth makes the mcp6281/1r/2/3/4/5 ideal for battery-powered applications. 4.1 rail-to-rail inputs 4.1.1 phase reversal the mcp6281/1r/2/3/4/5 op amp is designed to prevent phase reversal when the input pins exceed the supply voltages. figure 2-32 shows the input voltage exceeding the supply voltage without any phase reversal. 4.1.2 input voltage and current limits the esd protection on the inputs can be depicted as shown in figure 4-1 . this structure was chosen to protect the input transistors, and to minimize input bias current (i b ). the input esd diodes clamp the inputs when they try to go more than one diode drop below v ss . they also clamp any voltages that go too far above v dd ; their breakdown voltage is high enough to allow normal operation, and low enough to bypass quick esd events within the specified limits. figure 4-1: simplified analog input esd structures. in order to prevent damage and/or improper operation of these op amps, the circuit they are in must limit the currents and voltages at the v in + and v in C pins (see absolute maxi mum ratings ? at the beginning of section 1.0 electri cal characteristics ). figure 4-2 shows the recommended approach to protecting these inputs. the internal esd diodes prevent the input pins (v in + and v in C) from going too far below ground, and the resistors r 1 and r 2 limit the possible current drawn out of the input pins. diodes d 1 and d 2 prevent the input pins (v in + and v in C) from going too far above v dd , and dump any currents onto v dd . when implemented as shown, resistors r 1 and r 2 also limit the current through d 1 and d 2 . figure 4-2: protecting the analog inputs. it is also possible to connect the diodes to the left of resistors r 1 and r 2 . in this case, current through the diodes d 1 and d 2 needs to be limited by some other mechanism. the resistors th en serve as in-rush current limiters; the dc current into the input pins (v in + and v in C) should be very small. a significant amount of current can flow out of the inputs when the common mode voltage (v cm ) is below ground (v ss ); see figure 2-31 . applications that are high impedance may need to limit the usable voltage range. 4.1.3 normal operation the input stage of the mcp6281/1r/2/3/4/5 op amps use two differential cmos input stages in parallel. one operates at low common mode input voltage (v cm ), while the other operates at high v cm . with this topology, the device operates with v cm up to 0.3v above v dd and 0.3v below v ss . there is a transition in input behavior as v cm is changed. it occurs when v cm is near v dd C1.2v (see figure 2-3 and figure 2-6 ). for the best distortion performance with non-inverting gains, avoid these regions of operation. bond pad bond pad bond pad v dd v in + v ss input stage bond pad v in C v 1 mcp628x r 1 v dd d 1 r 1 > v ss C (minimum expected v 1 ) 2ma r 2 > v ss C (minimum expected v 2 ) 2ma v 2 r 2 d 2 r 3 downloaded from: http:///
? 2008 microchip technology inc. ds21811e-page 13 mcp6281/1r/2/3/4/5 4.2 rail-to-rail output the output voltage range of the mcp6281/1r/2/3/4/5 op amp is v dd C15mv (min.) and v ss +15mv (max.) when r l =10k is connected to v dd /2 and v dd = 5.5v. refer to figure 2-16 for more information. 4.3 capacitive loads driving large capacitive loads can cause stability problems for voltage feedback op amps. as the load capacitance increases, the feedback loops phase margin decreases and the closed-loop bandwidth is reduced. this produces gain peaking in the frequency response, with overshoot and ringing in the step response. a unity-gain buffer (g = +1) is the most sensitive to capacitive loads, though all gains show the same general behavior. when driving large capacitive loads with these op amps (e.g., > 100 pf when g = +1), a small series resistor at the output (r iso in figure 4-3 ) improves the feedback loops phase margin (stability) by making the output load resistive at higher frequencies. the bandwidth will generally be lower than the bandwidth with no capacitive load. figure 4-3: output resistor, r iso stabilizes large capacitive loads. figure 4-4 gives recommended r iso values for differ- ent capacitive loads and gains. the x-axis is the normalized load capacitance (c l /g n ), where g n is the circuit's noise gain. for non-inverting gains, g n and the signal gain are equal. for inverting gains, g n is 1+|signal gain| (e.g., -1 v/v gives g n = +2 v/v). figure 4-4: recommended r iso values for capacitive loads. after selecting r iso for your circuit, double-check the resulting frequency response peaking and step response overshoot. modify r iso 's value until the response is reasonable. bench evaluation and simula- tions with the mcp6281/1r/2/3/4/5 spice macro model are helpful. 4.4 mcp628x chip select (cs ) the mcp6283 and mcp6285 are single and dual op amps with chip select (cs ), respectively. when cs is pulled high, the supply current drops to 0.7 a (typical) and flows through the cs pin to v ss . when this hap- pens, the amplifier output is put into a high-impedance state. by pulling cs low, the amplifier is enabled. the cs pin has an internal 5 m (typical) pull-down resistor connected to v ss , so it will go low if the cs pin is left floating. figure 1-1 shows the output voltage and supply current response to a cs pulse. 4.5 cascaded dual op amps (mcp6285) the mcp6285 is a dual op amp with chip select (cs ). the chip select input is available on what would be the non-inverting input of a standard dual op amp (pin 5). this pin is available because the output of op amp a connects to the non-inverting input of op amp b, as shown in figure 4-5 . the chip select input, which can be connected to a microcon troller i/o line, puts the device in low-power mode. refer to section 4.4 mcp628x chip select (cs) . figure 4-5: cascaded gain amplifier. the output of op amp a is loaded by the input imped- ance of op amp b, which is typically 10 13 || 6pf, as specified in the dc specification table (refer to section 4.3 capacitive loads for further details regarding capacitive loads). the common mode input range of these op amps is specified in the data sheet as v ss C 300 mv and v dd + 300 mv. however, since the output of op amp a is limited to v ol and v oh (20 mv from the rails with a 10 k load), the non-inverting input range of op amp b is limited to the common mode input range of v ss + 20 mv and v dd C20mv. v in r iso v out c l C + mcp628x 10 100 1,000 10 100 1,000 10,000 normalized load capacitance; c l / g n (pf) recommended r iso ( : ) g n = 1 v/v g n = 2 v/v g n t 4 v/v a b cs 23 5 6 7 v ina + v outb mcp6285 1 v ina C v outa /v inb + v inb C downloaded from: http:///
mcp6281/1r/2/3/4/5 ds21811e-page 14 ? 2008 microchip technology inc. 4.6 supply bypass with this family of operat ional amplifiers, the power supply pin (v dd for single-supply) should have a local bypass capacitor (i.e., 0.01 f to 0.1 f) within 2 mm for good, high-frequency performance. it also needs a bulk capacitor (i.e., 1 f or larger) within 100 mm to provide large, slow currents. this bulk capacitor can be shared with nearby analog parts. 4.7 unused op amps an unused op amp in a quad package (mcp6284) should be configured as shown in figure 4-6 . these circuits prevent the output from toggling and causing crosstalk. circuits a sets the op amp at its minimum noise gain. the resistor divider produces any desired reference voltage within the ou tput voltage range of the op amp; the op amp buffers that reference voltage. circuit b uses the minimum number of components and operates as a comparator, but it may draw more current. figure 4-6: unused op amps. 4.8 pcb surface leakage in applications where low input bias current is critical, printed circuit board (pcb) surface-leakage effects need to be considered. surface leakage is caused by humidity, dust or other contamination on the board. under low humidity conditions, a typical resistance between nearby traces is 10 12 . a 5v difference would cause 5 pa of current to flow , which is greater than the mcp6281/1r/2/3/4/5 familys bias current at +25c (1 pa, typical). the easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). the guard ring is biased at the same voltage as the sensitive pin. an example of this type of layout is shown in figure 4-7 . figure 4-7: example guard ring layout for inverting gain. 1. for inverting gain and transimpedance amplifiers (convert current to voltage, such as photo detectors): a. connect the guard ring to the non-inverting input pin (v in +). this biases the guard ring to the same reference voltage as the op amp (e.g., v dd /2 or ground). b. connect the inverting pin (v in C) to the input with a wire that does not touch the pcb surface. 2. non-inverting gain and unity-gain buffer: a. connect the non-inverting pin (v in +) to the input with a wire that does not touch the pcb surface. b. connect the guard ring to the inverting input pin (v in C). this biases the guard ring to the common mode input voltage. v dd v dd ? mcp6284 (a) ? mcp6284 (b) r 1 r 2 v dd v ref v ref v dd r 2 r 1 r 2 + ------------------ ? = guard ring v ss v in Cv in + downloaded from: http:///
? 2008 microchip technology inc. ds21811e-page 15 mcp6281/1r/2/3/4/5 4.9 application circuits 4.9.1 sallen-key high-pass filter the mcp6281/1r/2/3/4/5 op amps can be used in active-filter applications. figure 4-8 shows a second- order sallen-key high-pass filter with a gain of 1. the output bias voltage is set by the v dd /2 reference, which can be changed to any voltage within the output voltage range. figure 4-8: sallen-key high-pass filter. this filter, and others, can be designed using microchips design aids; see section 5.2 filterlab? software and section 5.3 mindi? circuit designer & simulator . 4.9.2 inverting miller integrator analog integrators are used in filters, control loops and measurement circuits. figure 4-9 shows the most common implementation, the inverting miller integrator. the non-inverting input is at v dd /2 so that the op amp properly biases up. the switch (sw) is used to zero the output in some applications. other applications use a feedback loop to keep the output within its linear range of operation. figure 4-9: miller integrator. 4.9.3 cascaded op amp applications the mcp6285 provides the flexibility of low-power mode for dual op amps in an 8-pin package. the mcp6285 eliminates the added cost and space in battery-powered applications by using two single op amps with chip select lines or a 10-pin device with one chip select line for both op amps. since the two op amps are internally cascaded, this device cannot be used in circuits that require active or passive elements between the two op amps. however, there are several applications where this op amp configuration with chip select line becomes suitable. the circuits below show possible applications for this device. 4.9.3.1 load isolation with the cascaded op amp configuration, op amp b can be used to isolate the load from op amp a. in applica- tions where op amp a is driving capacitive or low resis- tance loads in the feedback loop (such as an integrator circuit or filter circuit), the op amp may not have sufficient source current to drive the load. in this case, op amp b can be used as a buffer. figure 4-10: isolating the load with a buffer. 4.9.3.2 cascaded gain figure 4-11 shows a cascaded gain circuit configura- tion with chip select. op amps a and b are configured in a non-inverting amplifier configuration. in this configuration, it is important to note that the input offset voltage of op amp a is amplified by the gain of op amp a and b, as shown below: therefore, it is recommend ed to set most of the gain with op amp a and use op amp b with relatively small gain (e.g., a unity-gain buffer). mcp6281 v out v in v dd /2 r 2 r 1 c 2 c 1 + C mcp6281 v out v in v dd /2 rc v out v in = 1 src sw + C a b mcp6285 cs v outb load v out v in g a g b v osa g a g b v osb g b + + = where: g a = op amp a gain g b = op amp b gain v osa = op amp a input offset voltage v osb = op amp b input offset voltage downloaded from: http:///
mcp6281/1r/2/3/4/5 ds21811e-page 16 ? 2008 microchip technology inc. figure 4-11: cascaded gain circuit configuration. 4.9.3.3 difference amplifier figure 4-12 shows op amp a configured as a difference amplifier with chip select. in this configuration, it is recommended to use well-matched resistors (e.g., 0.1%) to increase the common mode rejection ratio (cmrr). op amp b can be used to provide additional gain and isolate the load from the difference amplifier. figure 4-12: difference amplifier circuit. 4.9.3.4 buffered non-inverting integrator figure 4-13 shows a lossy non-inverting integrator that is buffered and has a chip select input. op amp a is configured as a non-inverting integrator. in this config- uration, matching the impedance at each input is recommended. r f is used to provide a feedback loop at frequencies << 1/(2 r 1 c 1 ) and makes this a lossy integrator (it has a finite gain at dc). op amp b is used to isolate the load from the integrator. figure 4-13: buffered non-inverting integrator with chip select. 4.9.3.5 inverting int egrator with active compensation and chip select figure 4-14 uses an active compensator (op amp b) to compensate for the non-ideal op amp characteristics introduced at higher frequencies. this circuit uses op amp b as a unity-gain buffer to isolate the integration capacitor c 1 from op amp a and drives the capacitor with low-impedance source. since both op amps are matched very well, they provide a higher quality integrator. figure 4-14: integrator circuit with active compensation. 4.9.3.6 second-order mfb low-pass filter with an extra pole-zero pair figure 4-15 is a second-order multiple feedback low- pass filter with chip select. use the filterlab ? software from microchip to determine the r and c values for the op amp as second-order filter. op amp b can be used to add a pole-zero pair using c 3 , r 6 , and r 7 . a b cs r 4 r 3 r 2 r 1 v in v out mcp6285 a b cs r 2 r 1 v in2 v in1 r 2 r 1 v out r 4 r 3 mcp6285 a b cs r f c 1 r 2 c 2 r 1 v in v out mcp6285 r 1 c 1 r 2 r f || () c 2 = a cs b v in v out r 1 c 1 mcp6285 downloaded from: http:///
? 2008 microchip technology inc. ds21811e-page 17 mcp6281/1r/2/3/4/5 figure 4-15: second-order multiple feedback low-pass filter with an extra pole-zero pair. 4.9.3.7 second-order sallen-key low-pass filter with an extra pole-zero pair figure 4-16 is a second-order sallen-key low-pass filter with chip sele ct. use the filterlab ? software from microchip to determine the r and c values for the op amp as second-order filter. op amp b can be used to add a pole-zero pair using c 3 , r 5 and r 6 . figure 4-16: second-order sallen-key low-pass filter wit h an extra pole-zero pair and chip select. 4.9.3.8 capacitorless second-order low-pass filter with chip select the low-pass filter shown in figure 4-17 does not require external capacitors and uses only three exter- nal resistors; the op amp's gbwp sets the corner frequency. r 1 and r 2 are used to set the circuit gain and r 3 is used to set the q. to avoid gain peaking in the frequency response, q needs to be low (lower values need to be selected for r 3 ). note that the ampli- fier bandwidth varies greatly over temperature and process. however, this c onfiguration provides a low- cost solution for applications with high bandwidth requirements. figure 4-17: capacitorless second-order low-pass filter wit h chip select. a b cs r 1 c 1 r 5 v in v out c 2 r 4 r 3 r 2 r 6 c 3 mcp6285 r 7 a b cs r 2 c 1 r 1 v in v out r 4 r 3 c 2 c 3 r 5 mcp6285 r 6 a b cs v ref v in v out r 2 r 1 r 3 mcp6285 downloaded from: http:///
mcp6281/1r/2/3/4/5 ds21811e-page 18 ? 2008 microchip technology inc. 5.0 design aids microchip provides the basic design tools needed for the mcp6281/1r/2/3/4/5 family of op amps. 5.1 spice macro model the latest spice macro model for the mcp6281/1r/2/ 3/4/5 op amps is available on the microchip web site at www.microchip.com. this model is intended to be an initial design tool that works well in the op amps linear region of operation over t he temperature range. see the model file for information on its capabilities. bench testing is a very important part of any design and cannot be replaced with simulations. also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 5.2 filterlab ? software microchips filterlab ? software is an innovative software tool that simplifies analog active filter (using op amps) design. available at no cost from the microchip web site at www.m icrochip.com/filterlab, the filterlab design tool prov ides full schematic diagrams of the filter circuit with component values. it also outputs the filter circuit in spice format, which can be used with the macro model to simulate actual filter performance. 5.3 mindi? circuit designer & simulator microchips mindi? circuit designer & simulator aids in the design of various circuits useful for active filter, amplifier and power-management applications. it is a free online circuit designer & simulator available from the microchip web site at www.microchip.com/mindi. this interactive circuit designer & simulator enables designers to quickly generate circuit diagrams, simu- late circuits. circuits developed using the mindi circuit designer & simulator can be downloaded to a personal computer or workstation. 5.4 maps (microchip advanced part selector) maps is a software tool that helps semiconductor professionals efficiently id entify microchip devices that fit a particular design requirement. available at no cost from the microchip web site at www.microchip.com/ maps, the maps is an over all selection tool for microchips product portfolio that includes analog, memory, mcus and dscs. using this tool you can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. helpful links are also provided for data sheets, purchase, and sampling of microchip parts. 5.5 analog demonstration and evaluation boards microchip offers a broad spectrum of analog demon- stration and evaluation boar ds that are designed to help you achieve faster time to market. for a complete listing of these boards and their corresponding users guides and technical information, visit the microchip web site at www.microchip.com/analogtools. two of our boards that are especially useful are: p/n soic8ev: 8-pin soic/msop/tssop/dip evaluation board p/n soic14ev: 14-pin soic/tssop/dip evaluation board 5.6 application notes the following microchip application notes are avail- able on the microchip web site at www.microchip. com/ appnotes and are recommended as supplemental ref- erence resources. adn003: select the right operational amplifier for your filtering circuits, ds21821 an722: operational amplifier topologies and dc specifications, ds00722 an723: operational amplifier ac specifications and applications, ds00723 an884: driving capacitive loads with op amps, ds00884 an990: analog sensor conditioning circuits C an overview, ds00990 these application notes and others are listed in the design guide: signal chain design guide, ds21825 downloaded from: http:///
? 2008 microchip technology inc. ds21811e-page 19 mcp6281/1r/2/3/4/5 6.0 packaging information 6.1 package marking information xxxxxxxxxxxxxnnn yyww 8-lead pdip (300 mil) example: mcp6281 e/p256 0722 8-lead msop xxxxxx ywwnnn 6281e 722256 5-lead sot-23 ( mcp6281 and mcp6281r ) example: xxnn ch25 device code mcp6281 chnn mcp6281r eunn note: applies to 5-lead sot-23. 6-lead sot-23 ( mcp6283 ) example: xxnn cl25 example: legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part nu mber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e mcp6281 e/p 256 0722 3 e or downloaded from: http:///
mcp6281/1r/2/3/4/5 ds21811e-page 20 ? 2008 microchip technology inc. package marking information (continued) 14-lead pdip (300 mil) (mcp6284) example: 14-lead tssop (mcp6284) example: 14-lead soic (150 mil) (mcp6284) example: xxxxxxxxxxxxxx xxxxxxxxxxxxxx yywwnnn xxxxxxxxxx yywwnnn xxxxxx yyww nnn mcp6284 -e/p 0722256 6284 est 0437 256 xxxxxxxxxx mcp6284 esl 0722256 8-lead soic (150 mil) example: xxxxxxxx xxxxyyww nnn mcp6281 e/sn0722 256 mcp6281 e sn 0722 256 or 3 e mcp6284 0722256 e/p 3 e or mcp6284 0722256 e/sl ^^ or 3 e downloaded from: http:///
? 2008 microchip technology inc. ds21811e-page 21 mcp6281/1r/2/3/4/5 5-lead plastic small outline transistor (ot) [sot-23] notes: 1. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.127 mm per side. 2. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 5 lead pitch e 0.95 bsc outside lead pitch e1 1.90 bsc overall height a 0.90 C 1.45 molded package thickness a2 0.89 C 1.30 standoff a1 0.00 C 0.15 overall width e 2.20 C 3.20 molded package width e1 1.30 C 1.80 overall length d 2.70 C 3.10 foot length l 0.10 C 0.60 footprint l1 0.35 C 0.80 foot angle 0 C 30 lead thickness c 0.08 C 0.26 lead width b 0.20 C 0.51 n b e e1 d 1 2 3 e e 1 a a1 a2 c l l1 microchip technology drawing c04-091b downloaded from: http:///
mcp6281/1r/2/3/4/5 ds21811e-page 22 ? 2008 microchip technology inc. 6-lead plastic small outline transistor (ch) [sot-23] notes: 1. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.127 mm per side. 2. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 6 pitch e 0.95 bsc outside lead pitch e1 1.90 bsc overall height a 0.90 C 1.45 molded package thickness a2 0.89 C 1.30 standoff a1 0.00 C 0.15 overall width e 2.20 C 3.20 molded package width e1 1.30 C 1.80 overall length d 2.70 C 3.10 foot length l 0.10 C 0.60 footprint l1 0.35 C 0.80 foot angle 0 C 30 lead thickness c 0.08 C 0.26 lead width b 0.20 C 0.51 b e 4 n e1 pin 1 id by laser mark d 1 2 3 e e 1 a a1 a2 c l l1 microchip technology drawing c04-028b downloaded from: http:///
? 2008 microchip technology inc. ds21811e-page 23 mcp6281/1r/2/3/4/5 8-lead plastic micro small outline package (ms) [msop] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15 mm per side. 3. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 8 pitch e 0.65 bsc overall height a C C 1.10 molded package thickness a2 0.75 0.85 0.95 standoff a1 0.00 C 0.15 overall width e 4.90 bsc molded package width e1 3.00 bsc overall length d 3.00 bsc foot length l 0.40 0.60 0.80 footprint l1 0.95 ref foot angle 0 C 8 lead thickness c 0.08 C 0.23 lead width b 0.22 C 0.40 d n e e1 note 1 1 2 e b a a1 a2 c l1 l microchip technology drawing c04-111b downloaded from: http:///
mcp6281/1r/2/3/4/5 ds21811e-page 24 ? 2008 microchip technology inc. 8-lead plastic dual in-line (p) C 300 mil body [pdip] notes: 1. pin 1 visual index feature may vary, but must be located with the hatched area. 2. significant characteristic. 3. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010" per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units inches dimension limits min nom max number of pins n 8 pitch e .100 bsc top to seating plane a C C .210 molded package thickness a2 .115 .130 .195 base to seating plane a1 .015 C C shoulder to shoulder width e .290 .310 .325 molded package width e1 .240 .250 .280 overall length d .348 .365 .400 tip to seating plane l .115 .130 .150 lead thickness c .008 .010 .015 upper lead width b1 .040 .060 .070 lower lead width b .014 .018 .022 overall row spacing eb C C .430 n e1 note 1 d 12 3 a a1 a2 l b1 b e e e b c microchip technology drawing c04-018b downloaded from: http:///
? 2008 microchip technology inc. ds21811e-page 25 mcp6281/1r/2/3/4/5 14-lead plastic dual in-line (p) C 300 mil body [pdip] notes: 1. pin 1 visual index feature may vary, but must be located with the hatched area. 2. significant characteristic. 3. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010" per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units inches dimension limits min nom max number of pins n 14 pitch e .100 bsc top to seating plane a C C .210 molded package thickness a2 .115 .130 .195 base to seating plane a1 .015 C C shoulder to shoulder width e .290 .310 .325 molded package width e1 .240 .250 .280 overall length d .735 .750 .775 tip to seating plane l .115 .130 .150 lead thickness c .008 .010 .015 upper lead width b1 .045 .060 .070 lower lead width b .014 .018 .022 overall row spacing eb C C .430 n e1 d note 1 12 3 e c e b a2 l a a1 b1 b e microchip technology drawing c04-005b downloaded from: http:///
mcp6281/1r/2/3/4/5 ds21811e-page 26 ? 2008 microchip technology inc. 8-lead plastic small outline (sn) C narrow, 3.90 mm body [soic] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. significant characteristic. 3. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15 mm per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 8 pitch e 1.27 bsc overall height a C C 1.75 molded package thickness a2 1.25 C C standoff a1 0.10 C 0.25 overall width e 6.00 bsc molded package width e1 3.90 bsc overall length d 4.90 bsc chamfer (optional) h 0.25 C 0.50 foot length l 0.40 C 1.27 footprint l1 1.04 ref foot angle 0 C 8 lead thickness c 0.17 C 0.25 lead width b 0.31 C 0.51 mold draft angle top 5 C 15 mold draft angle bottom 5 C 15 d n e e e1 note 1 12 3 b a a1 a2 l l1 c h h microchip technology drawing c04-057b downloaded from: http:///
? 2008 microchip technology inc. ds21811e-page 27 mcp6281/1r/2/3/4/5

!"#$% &

downloaded from: http:///
mcp6281/1r/2/3/4/5 ds21811e-page 28 ? 2008 microchip technology inc. 14-lead plastic small outline (sl) C narrow, 3.90 mm body [soic] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. significant characteristic. 3. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15 mm per side. 4. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 14 pitch e 1.27 bsc overall height a C C 1.75 molded package thickness a2 1.25 C C standoff a1 0.10 C 0.25 overall width e 6.00 bsc molded package width e1 3.90 bsc overall length d 8.65 bsc chamfer (optional) h 0.25 C 0.50 foot length l 0.40 C 1.27 footprint l1 1.04 ref foot angle 0 C 8 lead thickness c 0.17 C 0.25 lead width b 0.31 C 0.51 mold draft angle top 5 C 15 mold draft angle bottom 5 C 15 note 1 n d e e1 1 2 3 b e a a1 a2 l l1 c h h microchip technology drawing c04-065b downloaded from: http:///
? 2008 microchip technology inc. ds21811e-page 29 mcp6281/1r/2/3/4/5 14-lead plastic thin shrink small outline (st) C 4.4 mm body [tssop] notes: 1. pin 1 visual index feature may vary, but must be located within the hatched area. 2. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15 mm per side. 3. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. ref: reference dimension, usually without tolerance, for information purposes only. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 14 pitch e 0.65 bsc overall height a C C 1.20 molded package thickness a2 0.80 1.00 1.05 standoff a1 0.05 C 0.15 overall width e 6.40 bsc molded package width e1 4.30 4.40 4.50 molded package length d 4.90 5.00 5.10 foot length l 0.45 0.60 0.75 footprint l1 1.00 ref foot angle 0 C 8 lead thickness c 0.09 C 0.20 lead width b 0.19 C 0.30 note 1 d n e e1 1 2 e b c a a1 a2 l1 l microchip technology drawing c04-087b downloaded from: http:///
mcp6281/1r/2/3/4/5 ds21811e-page 30 ? 2008 microchip technology inc. notes: downloaded from: http:///
? 2008 microchip technology inc. ds21811e-page 31 mcp6281/1r/2/3/4/5 appendix a: revision history revision e (february 2008) the following is the list of modifications: 1. updated notes to section 1.0 electrical char- acteristics . 2. increased absolute maximum voltage range of input pins. increased maximum operating supply voltage (v dd ). 3. added section 1.1 test circuits . 4. added figure 2-32. 5. updated table 3-1 and table 3-2 in section 3.0 pin descriptions . 6. added section 4.1.1 phase reversal , section 4.1.2 input voltage and current limits , and section 4.1.3 normal opera- tion . 7. added section 4.7 unused op amps . 8. updated section 5.0 design aids . 9. updated package outline drawings in section 6.0 packaging information . revision d (december 2004) the following is the list of modifications: 1. added sot-23-5 packages for the mcp6281 and mcp6281r single op amps. 2. added sot-23-6 package for the mcp6283 single op amp. 3. added section 3.0 pin descriptions . 4. corrected application circuits ( section 4.9 application circuits ). 5. added sot-23-5 and sot-23-6 packages and corrected package marking information ( section 6.0 packaging information ). 6. added appendix a: revision history. revision c (june 2004) the following is the list of modifications: 1. undocumented changes. revision b (october 2003) the following is the list of modifications: 1. undocumented changes. revision a (june 2003) original data sheet release. downloaded from: http:///
mcp6281/1r/2/3/4/5 ds21811e-page 32 ? 2008 microchip technology inc. notes: downloaded from: http:///
? 2008 microchip technology inc. ds21811e-page 33 mcp6281/1r/2/3/4/5 product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . device: mcp6281: single op amp mcp6281t: single op amp (tape and reel) (soic, msop, sot-23-5) mcp6281rt: single op amp (tape and reel) (sot-23-5) mcp6282: dual op amp mcp6282t: dual op amp (tape and reel) (soic, msop) mcp6283: single op amp with c s mcp6283t: single op amp with c s (tape and reel) (soic, msop, sot-23-6) mcp6284: quad op amp mcp6284t: quad op amp (tape and reel) (soic, tssop) mcp6285: dual op amp with c s mcp6285t: dual op amp with c s (tape and reel) (soic, msop) temperature range: e = -40c to +125c package: ch = plastic small outline transistor (sot-23), 6-lead (mcp6283 only) ms = plastic msop, 8-lead p = plastic dip (300 mil body), 8-lead, 14-lead ot = plastic small outline transistor (sot-23), 5-lead (mcp6281, mcp6281r only) sl = plastic soic (3.90 mm body), 14-lead sn = plastic soic, (3.90 mm body), 8-lead st = plastic tssop (4.4 mm body), 14-lead part no. x /xx package temperature range device examples: a) mcp6281-e/sn: extended temperature, 8ld soic package. b) mcp6281-e/ms: extended temperature, 8ld msop package. c) mcp6281-e/p: extended temperature, 8ld pdip package. d) mcp6281t-e/ot: tape and reel, extended temperature, 5ld sot-23 package. e) mcp6281rt-e/ot: tape and reel, extended temperature, 5ld sot-23 package. a) mcp6282-e/sn: extended temperature, 8ld soic package. b) mcp6282-e/ms: extended temperature, 8ld msop package. c) mcp6282-e/p: extended temperature, 8ld pdip package. d) mcp6282t-e/sn: tape and reel, extended temperature, 8ld soic package. a) mcp6283-e/sn: extended temperature, 8ld soic package. b) mcp6283-e/ms: extended temperature, 8ld msop package. c) mcp6283-e/p: extended temperature, 8ld pdip package. d) mcp6283t-e/ch: tape and reel, extended temperature, 6ld sot-23 package. a) mcp6284-e/p: extended temperature, 14ld pdip package. b) mcp6284t-e/sl: tape and reel, extended temperature, 14ld soic package. c) mcp6284-e/sl: extended temperature, 14ld soic package. d) mcp6284-e/st: extended temperature, 14ld tssop package. a) mcp6285-e/sn: extended temperature, 8ld soic package. b) mcp6285-e/ms: extended temperature, 8ld msop package. c) mcp6285-e/p: extended temperature, 8ld pdip package. d) mcp6285t-e/sn: tape and reel, extended temperature, 8ld soic package. C downloaded from: http:///
mcp6281/1r/2/3/4/5 ds21811e-page 34 ? 2008 microchip technology inc. notes: downloaded from: http:///
? 2008 microchip technology inc. ds21811e-page 35 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pro mate, rfpic and smartshunt are registered trademarks of microchip te chnology incorporated in the u.s.a. and other countries. filterlab, linear active thermistor, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered tradema rks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, application maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, pickit, picdem, picdem.net, pictail, pic 32 logo, powercal, powerinfo, powermate, powertool, real ice, rflab, select mode, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2008, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchips c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the companys quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperi pherals, nonvolatile memory and analog products. in addition, microchips quality system for the design and manufacture of development systems is iso 9001:2000 certified. downloaded from: http:///
ds21811e-page 36 ? 2008 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-4182-8400 fax: 91-80-4182-8422 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-572-9526 fax: 886-3-572-6459 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 01/02/08 downloaded from: http:///

▲Up To Search▲

Price & Availability of MCP6284T-ESLDAA

	To Download MCP6284T-ESLDAA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .